How to find out the definition of the variable MAKE












1














Haven't been using make for a while. But just got a project from a 10 years old compiler using Ubuntu.



I am looking at the makefile and trying to find out which compiler it is using.
${MAKE} is used in the file.
But where can I find out the definition of MAKE.
Thanks










share|improve this question





























    1














    Haven't been using make for a while. But just got a project from a 10 years old compiler using Ubuntu.



    I am looking at the makefile and trying to find out which compiler it is using.
    ${MAKE} is used in the file.
    But where can I find out the definition of MAKE.
    Thanks










    share|improve this question



























      1












      1








      1







      Haven't been using make for a while. But just got a project from a 10 years old compiler using Ubuntu.



      I am looking at the makefile and trying to find out which compiler it is using.
      ${MAKE} is used in the file.
      But where can I find out the definition of MAKE.
      Thanks










      share|improve this question















      Haven't been using make for a while. But just got a project from a 10 years old compiler using Ubuntu.



      I am looking at the makefile and trying to find out which compiler it is using.
      ${MAKE} is used in the file.
      But where can I find out the definition of MAKE.
      Thanks







      makefile gnu-make






      share|improve this question















      share|improve this question













      share|improve this question




      share|improve this question








      edited Nov 22 at 15:47









      ネロク

      10.5k32140




      10.5k32140










      asked Nov 22 at 15:28









      Paul

      250211




      250211
























          1 Answer
          1






          active

          oldest

          votes


















          1














          You could simply use both the info and value built-in functions inside your makefile:



          $(info MAKE: $(value MAKE))


          This will work if MAKE is a recursively expanded variable, which it is by default. Otherwise, if MAKE were a simply expanded variable, you will see the expansion that was done at the moment of evaluating MAKE's definition (i.e., the same as $(MAKE)).





          A better approach, which is independent of the flavour of the variable, would be to run make with the option -p and look at the definition of MAKE, e.g.:



          make -p | grep 'MAKE ='




          You will probably find out that MAKE is defined as:



          MAKE = $(MAKE_COMMAND)


          and MAKE_COMMAND, which is another variable (this time, a simply expanded one), may be in turn defined as:



          MAKE_COMMAND := make





          share|improve this answer























          • Thank you! Now I understand it better. I have the compiler and linker, the .exe file. I can just use Eclipse to build the project right? The whole purpose to get a "linux" installed on the computer is to run "make" because make is able to interpret the Makefile. And the Eclipse I installed with C/C++ support is able to interpret the Makefile.
            – Paul
            Nov 22 at 19:43












          • GNU Make is also available for Windows. Search for MinGW.
            – ネロク
            Nov 22 at 19:47










          • Thanks. So it doesn't make sense anymore to install linux (cygwin or WSL) on windows computer just for "make".
            – Paul
            Nov 22 at 21:23











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          1 Answer
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          1 Answer
          1






          active

          oldest

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          active

          oldest

          votes






          active

          oldest

          votes









          1














          You could simply use both the info and value built-in functions inside your makefile:



          $(info MAKE: $(value MAKE))


          This will work if MAKE is a recursively expanded variable, which it is by default. Otherwise, if MAKE were a simply expanded variable, you will see the expansion that was done at the moment of evaluating MAKE's definition (i.e., the same as $(MAKE)).





          A better approach, which is independent of the flavour of the variable, would be to run make with the option -p and look at the definition of MAKE, e.g.:



          make -p | grep 'MAKE ='




          You will probably find out that MAKE is defined as:



          MAKE = $(MAKE_COMMAND)


          and MAKE_COMMAND, which is another variable (this time, a simply expanded one), may be in turn defined as:



          MAKE_COMMAND := make





          share|improve this answer























          • Thank you! Now I understand it better. I have the compiler and linker, the .exe file. I can just use Eclipse to build the project right? The whole purpose to get a "linux" installed on the computer is to run "make" because make is able to interpret the Makefile. And the Eclipse I installed with C/C++ support is able to interpret the Makefile.
            – Paul
            Nov 22 at 19:43












          • GNU Make is also available for Windows. Search for MinGW.
            – ネロク
            Nov 22 at 19:47










          • Thanks. So it doesn't make sense anymore to install linux (cygwin or WSL) on windows computer just for "make".
            – Paul
            Nov 22 at 21:23
















          1














          You could simply use both the info and value built-in functions inside your makefile:



          $(info MAKE: $(value MAKE))


          This will work if MAKE is a recursively expanded variable, which it is by default. Otherwise, if MAKE were a simply expanded variable, you will see the expansion that was done at the moment of evaluating MAKE's definition (i.e., the same as $(MAKE)).





          A better approach, which is independent of the flavour of the variable, would be to run make with the option -p and look at the definition of MAKE, e.g.:



          make -p | grep 'MAKE ='




          You will probably find out that MAKE is defined as:



          MAKE = $(MAKE_COMMAND)


          and MAKE_COMMAND, which is another variable (this time, a simply expanded one), may be in turn defined as:



          MAKE_COMMAND := make





          share|improve this answer























          • Thank you! Now I understand it better. I have the compiler and linker, the .exe file. I can just use Eclipse to build the project right? The whole purpose to get a "linux" installed on the computer is to run "make" because make is able to interpret the Makefile. And the Eclipse I installed with C/C++ support is able to interpret the Makefile.
            – Paul
            Nov 22 at 19:43












          • GNU Make is also available for Windows. Search for MinGW.
            – ネロク
            Nov 22 at 19:47










          • Thanks. So it doesn't make sense anymore to install linux (cygwin or WSL) on windows computer just for "make".
            – Paul
            Nov 22 at 21:23














          1












          1








          1






          You could simply use both the info and value built-in functions inside your makefile:



          $(info MAKE: $(value MAKE))


          This will work if MAKE is a recursively expanded variable, which it is by default. Otherwise, if MAKE were a simply expanded variable, you will see the expansion that was done at the moment of evaluating MAKE's definition (i.e., the same as $(MAKE)).





          A better approach, which is independent of the flavour of the variable, would be to run make with the option -p and look at the definition of MAKE, e.g.:



          make -p | grep 'MAKE ='




          You will probably find out that MAKE is defined as:



          MAKE = $(MAKE_COMMAND)


          and MAKE_COMMAND, which is another variable (this time, a simply expanded one), may be in turn defined as:



          MAKE_COMMAND := make





          share|improve this answer














          You could simply use both the info and value built-in functions inside your makefile:



          $(info MAKE: $(value MAKE))


          This will work if MAKE is a recursively expanded variable, which it is by default. Otherwise, if MAKE were a simply expanded variable, you will see the expansion that was done at the moment of evaluating MAKE's definition (i.e., the same as $(MAKE)).





          A better approach, which is independent of the flavour of the variable, would be to run make with the option -p and look at the definition of MAKE, e.g.:



          make -p | grep 'MAKE ='




          You will probably find out that MAKE is defined as:



          MAKE = $(MAKE_COMMAND)


          and MAKE_COMMAND, which is another variable (this time, a simply expanded one), may be in turn defined as:



          MAKE_COMMAND := make






          share|improve this answer














          share|improve this answer



          share|improve this answer








          edited Nov 22 at 15:59

























          answered Nov 22 at 15:31









          ネロク

          10.5k32140




          10.5k32140












          • Thank you! Now I understand it better. I have the compiler and linker, the .exe file. I can just use Eclipse to build the project right? The whole purpose to get a "linux" installed on the computer is to run "make" because make is able to interpret the Makefile. And the Eclipse I installed with C/C++ support is able to interpret the Makefile.
            – Paul
            Nov 22 at 19:43












          • GNU Make is also available for Windows. Search for MinGW.
            – ネロク
            Nov 22 at 19:47










          • Thanks. So it doesn't make sense anymore to install linux (cygwin or WSL) on windows computer just for "make".
            – Paul
            Nov 22 at 21:23


















          • Thank you! Now I understand it better. I have the compiler and linker, the .exe file. I can just use Eclipse to build the project right? The whole purpose to get a "linux" installed on the computer is to run "make" because make is able to interpret the Makefile. And the Eclipse I installed with C/C++ support is able to interpret the Makefile.
            – Paul
            Nov 22 at 19:43












          • GNU Make is also available for Windows. Search for MinGW.
            – ネロク
            Nov 22 at 19:47










          • Thanks. So it doesn't make sense anymore to install linux (cygwin or WSL) on windows computer just for "make".
            – Paul
            Nov 22 at 21:23
















          Thank you! Now I understand it better. I have the compiler and linker, the .exe file. I can just use Eclipse to build the project right? The whole purpose to get a "linux" installed on the computer is to run "make" because make is able to interpret the Makefile. And the Eclipse I installed with C/C++ support is able to interpret the Makefile.
          – Paul
          Nov 22 at 19:43






          Thank you! Now I understand it better. I have the compiler and linker, the .exe file. I can just use Eclipse to build the project right? The whole purpose to get a "linux" installed on the computer is to run "make" because make is able to interpret the Makefile. And the Eclipse I installed with C/C++ support is able to interpret the Makefile.
          – Paul
          Nov 22 at 19:43














          GNU Make is also available for Windows. Search for MinGW.
          – ネロク
          Nov 22 at 19:47




          GNU Make is also available for Windows. Search for MinGW.
          – ネロク
          Nov 22 at 19:47












          Thanks. So it doesn't make sense anymore to install linux (cygwin or WSL) on windows computer just for "make".
          – Paul
          Nov 22 at 21:23




          Thanks. So it doesn't make sense anymore to install linux (cygwin or WSL) on windows computer just for "make".
          – Paul
          Nov 22 at 21:23


















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