How to generate Verilog code with parametized modules in Chisel?












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The following module definition in chisel:



class Mux2 (width: Int = 4) extends Module


does not result in a Verilog module that is parametrized. The generated Verilog RTL will instead substitute the parameter value that the user instantiated the module with.



Is there a way to generate Verilog with actual parametrized module definitions.



module Mux2 #(parameter width = 4)


If there is no way to do this this would be a very useful feature to add.










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    1














    The following module definition in chisel:



    class Mux2 (width: Int = 4) extends Module


    does not result in a Verilog module that is parametrized. The generated Verilog RTL will instead substitute the parameter value that the user instantiated the module with.



    Is there a way to generate Verilog with actual parametrized module definitions.



    module Mux2 #(parameter width = 4)


    If there is no way to do this this would be a very useful feature to add.










    share|improve this question

























      1












      1








      1







      The following module definition in chisel:



      class Mux2 (width: Int = 4) extends Module


      does not result in a Verilog module that is parametrized. The generated Verilog RTL will instead substitute the parameter value that the user instantiated the module with.



      Is there a way to generate Verilog with actual parametrized module definitions.



      module Mux2 #(parameter width = 4)


      If there is no way to do this this would be a very useful feature to add.










      share|improve this question













      The following module definition in chisel:



      class Mux2 (width: Int = 4) extends Module


      does not result in a Verilog module that is parametrized. The generated Verilog RTL will instead substitute the parameter value that the user instantiated the module with.



      Is there a way to generate Verilog with actual parametrized module definitions.



      module Mux2 #(parameter width = 4)


      If there is no way to do this this would be a very useful feature to add.







      chisel






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      asked Nov 22 at 16:23









      caylus

      12115




      12115
























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          Unfortunately this is probably an impossible feature to add. Chisel is really just a Scala library of hardware primitives that enables you to write a Scala program to elaborate a circuit. Parameterization of Chisel generators is arbitrary Scala code which would be impossible to map to Verilog constructs in the general case. In fact, the primary utility of Chisel comes from enabling designers to use these higher-level constructs that do not exist in [synthesizable] Verilog (eg. object-oriented programming, functional programming).






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            Unfortunately this is probably an impossible feature to add. Chisel is really just a Scala library of hardware primitives that enables you to write a Scala program to elaborate a circuit. Parameterization of Chisel generators is arbitrary Scala code which would be impossible to map to Verilog constructs in the general case. In fact, the primary utility of Chisel comes from enabling designers to use these higher-level constructs that do not exist in [synthesizable] Verilog (eg. object-oriented programming, functional programming).






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              Unfortunately this is probably an impossible feature to add. Chisel is really just a Scala library of hardware primitives that enables you to write a Scala program to elaborate a circuit. Parameterization of Chisel generators is arbitrary Scala code which would be impossible to map to Verilog constructs in the general case. In fact, the primary utility of Chisel comes from enabling designers to use these higher-level constructs that do not exist in [synthesizable] Verilog (eg. object-oriented programming, functional programming).






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                Unfortunately this is probably an impossible feature to add. Chisel is really just a Scala library of hardware primitives that enables you to write a Scala program to elaborate a circuit. Parameterization of Chisel generators is arbitrary Scala code which would be impossible to map to Verilog constructs in the general case. In fact, the primary utility of Chisel comes from enabling designers to use these higher-level constructs that do not exist in [synthesizable] Verilog (eg. object-oriented programming, functional programming).






                share|improve this answer












                Unfortunately this is probably an impossible feature to add. Chisel is really just a Scala library of hardware primitives that enables you to write a Scala program to elaborate a circuit. Parameterization of Chisel generators is arbitrary Scala code which would be impossible to map to Verilog constructs in the general case. In fact, the primary utility of Chisel comes from enabling designers to use these higher-level constructs that do not exist in [synthesizable] Verilog (eg. object-oriented programming, functional programming).







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                answered Nov 26 at 19:53









                jkoenig

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