Pipelining in 24bit number*16 Bit Number multiplier











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I am implementing fir Filter which requires a 24*16 Bit multiplier. I have implemented the multiplier but in my design Timing constraints are not met. I want to do pipelining for efficient speed and Performance.
Can some one guide me where to Start?
I have used wallace tree reduction for partial products addition.
Thank you.










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  • VLSI Architecture of Pipelined Booth Wallace MAC Unit (A little research effort might be in order - found this by googling. This question appears off-topic here.)
    – user1155120
    Nov 22 at 6:31










  • Problem is still there?Will you elaborate how to put pipeline inmiddle of wallace tree reduction?
    – Zohaib Ramzan
    Nov 24 at 15:57















up vote
-1
down vote

favorite












I am implementing fir Filter which requires a 24*16 Bit multiplier. I have implemented the multiplier but in my design Timing constraints are not met. I want to do pipelining for efficient speed and Performance.
Can some one guide me where to Start?
I have used wallace tree reduction for partial products addition.
Thank you.










share|improve this question






















  • VLSI Architecture of Pipelined Booth Wallace MAC Unit (A little research effort might be in order - found this by googling. This question appears off-topic here.)
    – user1155120
    Nov 22 at 6:31










  • Problem is still there?Will you elaborate how to put pipeline inmiddle of wallace tree reduction?
    – Zohaib Ramzan
    Nov 24 at 15:57













up vote
-1
down vote

favorite









up vote
-1
down vote

favorite











I am implementing fir Filter which requires a 24*16 Bit multiplier. I have implemented the multiplier but in my design Timing constraints are not met. I want to do pipelining for efficient speed and Performance.
Can some one guide me where to Start?
I have used wallace tree reduction for partial products addition.
Thank you.










share|improve this question













I am implementing fir Filter which requires a 24*16 Bit multiplier. I have implemented the multiplier but in my design Timing constraints are not met. I want to do pipelining for efficient speed and Performance.
Can some one guide me where to Start?
I have used wallace tree reduction for partial products addition.
Thank you.







vhdl pipeline vlsi






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share|improve this question











share|improve this question




share|improve this question










asked Nov 21 at 17:41









Zohaib Ramzan

22




22












  • VLSI Architecture of Pipelined Booth Wallace MAC Unit (A little research effort might be in order - found this by googling. This question appears off-topic here.)
    – user1155120
    Nov 22 at 6:31










  • Problem is still there?Will you elaborate how to put pipeline inmiddle of wallace tree reduction?
    – Zohaib Ramzan
    Nov 24 at 15:57


















  • VLSI Architecture of Pipelined Booth Wallace MAC Unit (A little research effort might be in order - found this by googling. This question appears off-topic here.)
    – user1155120
    Nov 22 at 6:31










  • Problem is still there?Will you elaborate how to put pipeline inmiddle of wallace tree reduction?
    – Zohaib Ramzan
    Nov 24 at 15:57
















VLSI Architecture of Pipelined Booth Wallace MAC Unit (A little research effort might be in order - found this by googling. This question appears off-topic here.)
– user1155120
Nov 22 at 6:31




VLSI Architecture of Pipelined Booth Wallace MAC Unit (A little research effort might be in order - found this by googling. This question appears off-topic here.)
– user1155120
Nov 22 at 6:31












Problem is still there?Will you elaborate how to put pipeline inmiddle of wallace tree reduction?
– Zohaib Ramzan
Nov 24 at 15:57




Problem is still there?Will you elaborate how to put pipeline inmiddle of wallace tree reduction?
– Zohaib Ramzan
Nov 24 at 15:57

















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