Why doesn't my de-multiplexer with the selected signal assignment work?
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It might be a stupid question...
I want to make a de-multiplexer with one input: a , a byte and two outputs, x and y(also bytes).
there is also a signal input : s
The de-multiplexer should work with the selected signal assignment.
Whenever s is 1, x should be the value of a. When s is 0, the value of y should be the value of a.
with s select x <= a when '1';
with s select y <= a when '0';
when i put it in a process like this:
p1 : process (s,a)
with s select x <= a when '1';
with s select y <= a when '0';
end process;
I made a testbench and used it to test my dmux, when i trie to run it, it says that i didn't use al possibilities, but I did? Right?
Can anyone help me?
Thanks in advance
vhdl vivado test-bench
asked Nov 21 at 15:07
Worst
14
|
show 9 more comments
up vote
0
down vote
favorite
It might be a stupid question...
I want to make a de-multiplexer with one input: a , a byte and two outputs, x and y(also bytes).
there is also a signal input : s
The de-multiplexer should work with the selected signal assignment.
Whenever s is 1, x should be the value of a. When s is 0, the value of y should be the value of a.
with s select x <= a when '1';
with s select y <= a when '0';
when i put it in a process like this:
p1 : process (s,a)
with s select x <= a when '1';
with s select y <= a when '0';
end process;
I made a testbench and used it to test my dmux, when i trie to run it, it says that i didn't use al possibilities, but I did? Right?
Can anyone help me?
Thanks in advance
vhdl vivado test-bench
asked Nov 21 at 15:07
Worst
14
"doesn't work" isn't a a problem statement. Provide a Minimal, Complete, and Verifiable example including a description of the problem and the means to replicate it.
– user1155120
Nov 21 at 16:24
I edited my question with some extra info
– Worst
Nov 21 at 16:33
1
ok, i fixed it, I forgot the others statement...
– Worst
Nov 21 at 16:47
A selected signal assignment has an equivalent case statement, where all the choices must be covered. The base type of s isn't provided. If it's declared as type std_logic the base type is std_ulogic, a character enumeration type with possible values 'U', X', '0'. '1', 'Z', 'W', 'L', 'H', and '-'. What is the type of s? Are all the choices covered?
– user1155120
Nov 21 at 16:49
entity dmux is Port ( a : in std_logic_vector (7 downto 0); s : in std_logic; x : out std_logic_vector (7 downto 0); y : out std_logic_vector (7 downto 0) ); end dmux;
– Worst
Nov 21 at 17:03
|
show 9 more comments
up vote
0
down vote
favorite
up vote
0
down vote
favorite
It might be a stupid question...
I want to make a de-multiplexer with one input: a , a byte and two outputs, x and y(also bytes).
there is also a signal input : s
The de-multiplexer should work with the selected signal assignment.
Whenever s is 1, x should be the value of a. When s is 0, the value of y should be the value of a.
with s select x <= a when '1';
with s select y <= a when '0';
when i put it in a process like this:
p1 : process (s,a)
with s select x <= a when '1';
with s select y <= a when '0';
end process;
I made a testbench and used it to test my dmux, when i trie to run it, it says that i didn't use al possibilities, but I did? Right?
Can anyone help me?
Thanks in advance
vhdl vivado test-bench
asked Nov 21 at 15:07
Worst
14
It might be a stupid question...
I want to make a de-multiplexer with one input: a , a byte and two outputs, x and y(also bytes).
there is also a signal input : s
The de-multiplexer should work with the selected signal assignment.
Whenever s is 1, x should be the value of a. When s is 0, the value of y should be the value of a.
with s select x <= a when '1';
with s select y <= a when '0';
when i put it in a process like this:
p1 : process (s,a)
with s select x <= a when '1';
with s select y <= a when '0';
end process;
I made a testbench and used it to test my dmux, when i trie to run it, it says that i didn't use al possibilities, but I did? Right?
Can anyone help me?
Thanks in advance
vhdl vivado test-bench
vhdl vivado test-bench
asked Nov 21 at 15:07
Worst
14
asked Nov 21 at 15:07
Worst
14
edited Nov 21 at 17:11
asked Nov 21 at 15:07
Worst
14
asked Nov 21 at 15:07
Worst
14
asked Nov 21 at 15:07
Worst
14
14
"doesn't work" isn't a a problem statement. Provide a Minimal, Complete, and Verifiable example including a description of the problem and the means to replicate it.
– user1155120
Nov 21 at 16:24
I edited my question with some extra info
– Worst
Nov 21 at 16:33
1
ok, i fixed it, I forgot the others statement...
– Worst
Nov 21 at 16:47
A selected signal assignment has an equivalent case statement, where all the choices must be covered. The base type of s isn't provided. If it's declared as type std_logic the base type is std_ulogic, a character enumeration type with possible values 'U', X', '0'. '1', 'Z', 'W', 'L', 'H', and '-'. What is the type of s? Are all the choices covered?
– user1155120
Nov 21 at 16:49
entity dmux is Port ( a : in std_logic_vector (7 downto 0); s : in std_logic; x : out std_logic_vector (7 downto 0); y : out std_logic_vector (7 downto 0) ); end dmux;
– Worst
Nov 21 at 17:03
|
show 9 more comments
"doesn't work" isn't a a problem statement. Provide a Minimal, Complete, and Verifiable example including a description of the problem and the means to replicate it.
– user1155120
Nov 21 at 16:24
I edited my question with some extra info
– Worst
Nov 21 at 16:33
1
ok, i fixed it, I forgot the others statement...
– Worst
Nov 21 at 16:47
A selected signal assignment has an equivalent case statement, where all the choices must be covered. The base type of s isn't provided. If it's declared as type std_logic the base type is std_ulogic, a character enumeration type with possible values 'U', X', '0'. '1', 'Z', 'W', 'L', 'H', and '-'. What is the type of s? Are all the choices covered?
– user1155120
Nov 21 at 16:49
entity dmux is Port ( a : in std_logic_vector (7 downto 0); s : in std_logic; x : out std_logic_vector (7 downto 0); y : out std_logic_vector (7 downto 0) ); end dmux;
– Worst
Nov 21 at 17:03
"doesn't work" isn't a a problem statement. Provide a Minimal, Complete, and Verifiable example including a description of the problem and the means to replicate it.
– user1155120
Nov 21 at 16:24
"doesn't work" isn't a a problem statement. Provide a Minimal, Complete, and Verifiable example including a description of the problem and the means to replicate it.
– user1155120
Nov 21 at 16:24
I edited my question with some extra info
– Worst
Nov 21 at 16:33
I edited my question with some extra info
– Worst
Nov 21 at 16:33
1
1
ok, i fixed it, I forgot the others statement...
– Worst
Nov 21 at 16:47
ok, i fixed it, I forgot the others statement...
– Worst
Nov 21 at 16:47
A selected signal assignment has an equivalent case statement, where all the choices must be covered. The base type of s isn't provided. If it's declared as type std_logic the base type is std_ulogic, a character enumeration type with possible values 'U', X', '0'. '1', 'Z', 'W', 'L', 'H', and '-'. What is the type of s? Are all the choices covered?
– user1155120
Nov 21 at 16:49
A selected signal assignment has an equivalent case statement, where all the choices must be covered. The base type of s isn't provided. If it's declared as type std_logic the base type is std_ulogic, a character enumeration type with possible values 'U', X', '0'. '1', 'Z', 'W', 'L', 'H', and '-'. What is the type of s? Are all the choices covered?
– user1155120
Nov 21 at 16:49
entity dmux is Port ( a : in std_logic_vector (7 downto 0); s : in std_logic; x : out std_logic_vector (7 downto 0); y : out std_logic_vector (7 downto 0) ); end dmux;
– Worst
Nov 21 at 17:03
entity dmux is Port ( a : in std_logic_vector (7 downto 0); s : in std_logic; x : out std_logic_vector (7 downto 0); y : out std_logic_vector (7 downto 0) ); end dmux;
– Worst
Nov 21 at 17:03
|
show 9 more comments
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"doesn't work" isn't a a problem statement. Provide a Minimal, Complete, and Verifiable example including a description of the problem and the means to replicate it.
– user1155120
Nov 21 at 16:24
I edited my question with some extra info
– Worst
Nov 21 at 16:33
1
ok, i fixed it, I forgot the others statement...
– Worst
Nov 21 at 16:47
A selected signal assignment has an equivalent case statement, where all the choices must be covered. The base type of s isn't provided. If it's declared as type std_logic the base type is std_ulogic, a character enumeration type with possible values 'U', X', '0'. '1', 'Z', 'W', 'L', 'H', and '-'. What is the type of s? Are all the choices covered?
– user1155120
Nov 21 at 16:49
entity dmux is Port ( a : in std_logic_vector (7 downto 0); s : in std_logic; x : out std_logic_vector (7 downto 0); y : out std_logic_vector (7 downto 0) ); end dmux;
– Worst
Nov 21 at 17:03